MeitY aims to train 85,000 engineers on chip design in next 5 years

The Ministry of Electronics and Information Technology (MeitY) seeks to train more than 85,000 engineers on chip design by expanding the infrastructure available for the technology to 120 academic institutions across India in the next 5 years.

Under a special manpower development programme for Chips to System Design (SMDP-C2SD), the MeitY had accomplished a pilot deployment in 2021. A centralised design unit at the state-run Centre for Development of Advanced Computing (C-DAC) was enabled for remote access by over 50,000 engineering students for designing chips at 60 academic institutions.

Meity now aims to make accessible a centralised chip design infrastructure to be made available at the India Chip Centre setup at C-DAC to train over 85000 B Tech, M Tech, and Ph.D. students at 120 institutions across India in the chip design area for the following 5 years.

For making available the chip design infrastructure at the India Chip Centre of C-DAC, leading industry vendors from Electronic Design Automation (EDA), Electronic Computer-Aided Design (ECAD), IP Core, and the Design solutions Industry are being collaborated.

Specific joint arrangements are being made available with Synopsys, Siemens EDA, Silvaco Cadence Design Systems, and other top tool vendors, IP & design solution providers, and Fab aggregators.

As SemiconIndia 2022 ended successfully last week, most of the global semiconductor leaders like Intel, Micron, Qualcomm, LAM Research, etc not only stressed the contribution of their Indian research and development centres, which are now the biggest centres out of their headquarters locations but also recognised the semiconductor design strength in India, which now makes up for 20% of the world’s engineers.

At the Semicon India conference, Electronics and IT minister Ashwini Vaishnaw emphasised that India’s democracy and talent pool sets it apart from other nations fighting for chip sovereignty.

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