Ashwini Vaishnaw Reviews Progress of DLI-Backed Chip Designers

29 Jan 2026 CW Team

The DLI-supported firms are engaged across a wide spectrum of chip design areas, including system-on-chips and ASICs for surveillance and networking, RISC-V-based processors, AI-enabled low-power chips for IoT and edge applications, telecom and wireless chipsets, power management ICs and mixed-signal designs. These efforts extend to strategic sectors such as automotive, energy, space and defence. Advanced EDA tools provided under the scheme have enabled about 2.25 crore tool-hours of usage, involving nearly 67,000 students and more than 1,000 startup engineers.

Addressing stakeholders, the Minister said the Government’s ecosystem-led, long-term approach to semiconductors is delivering tangible outcomes. He noted that the programme, conceptualised in 2022 under the vision of Narendra Modi, aims to transform India from a services-led economy into a product nation by building the entire semiconductor value chain.

Highlighting the success of the DLI Scheme, Vaishnaw said 24 startups are currently supported, several of which have completed tape-outs, validated products and achieved market traction. He added that the Government now plans to scale up the initiative, targeting at least 50 fabless semiconductor companies in the next phase.

The Minister outlined a focused strategy across six key design domains—compute systems, RF and wireless, networking, power management, sensors and memory—describing them as foundational to modern electronics. He also referred to infrastructure support, with SCL Mohali enabling 180-nanometre tape-outs and the upcoming Dholera fab supporting nodes up to 28 nanometres.

Looking ahead, Vaishnaw said India aims to design and manufacture chips for nearly 70–75 per cent of domestic applications by 2029, with Semicon 2.0 charting a roadmap towards advanced nodes of 3 nanometres and 2 nanometres. He also announced that the Government will institute Deep Tech Awards in 2026 to recognise innovation in semiconductors, AI, biotechnology, space and other critical technologies.

Union Minister for Electronics and Information Technology Ashwini Vaishnaw recently interacted with semiconductor chip design companies approved under the Design Linked Incentive (DLI) Scheme of the Semicon India Programme in New Delhi. The interaction focused on assessing progress, reviewing design innovations and reaffirming the Government’s commitment to building a strong, indigenous semiconductor design ecosystem. The DLI-supported firms are engaged across a wide spectrum of chip design areas, including system-on-chips and ASICs for surveillance and networking, RISC-V-based processors, AI-enabled low-power chips for IoT and edge applications, telecom and wireless chipsets, power management ICs and mixed-signal designs. These efforts extend to strategic sectors such as automotive, energy, space and defence. Advanced EDA tools provided under the scheme have enabled about 2.25 crore tool-hours of usage, involving nearly 67,000 students and more than 1,000 startup engineers. Addressing stakeholders, the Minister said the Government’s ecosystem-led, long-term approach to semiconductors is delivering tangible outcomes. He noted that the programme, conceptualised in 2022 under the vision of Narendra Modi, aims to transform India from a services-led economy into a product nation by building the entire semiconductor value chain. Highlighting the success of the DLI Scheme, Vaishnaw said 24 startups are currently supported, several of which have completed tape-outs, validated products and achieved market traction. He added that the Government now plans to scale up the initiative, targeting at least 50 fabless semiconductor companies in the next phase. The Minister outlined a focused strategy across six key design domains—compute systems, RF and wireless, networking, power management, sensors and memory—describing them as foundational to modern electronics. He also referred to infrastructure support, with SCL Mohali enabling 180-nanometre tape-outs and the upcoming Dholera fab supporting nodes up to 28 nanometres. Looking ahead, Vaishnaw said India aims to design and manufacture chips for nearly 70–75 per cent of domestic applications by 2029, with Semicon 2.0 charting a roadmap towards advanced nodes of 3 nanometres and 2 nanometres. He also announced that the Government will institute Deep Tech Awards in 2026 to recognise innovation in semiconductors, AI, biotechnology, space and other critical technologies.

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