India Semiconductor Mission 2.0 Accelerates Domestic Chip Capacity

12 Feb 2026 CW Team

ISM 2.0 builds on earlier progress, where an incentive framework of Rs 760 bn supported silicon fabs, compound semiconductor facilities and chip design. As of December 2025, ten projects with total investment of Rs 1.6 trillion (tn) have been approved across six states, covering fabrication, advanced packaging and assembly and testing infrastructure. The roadmap targets advanced nodes and aims to position India among leading semiconductor nations by 2035.

For 2026–27 the modified programme for semiconductor and display manufacturing has a total financial outlay of Rs 80 bn, aiming to accelerate capital investment, generate high quality employment and expand domestic fabrication, packaging and design capabilities. The modified fab scheme expects support for one fab with investment of Rs 40 bn and employment of 1,500 persons, while compound semiconductor and ATMP schemes envisage unit investments of Rs 110 bn and employment of 3,000 persons. The design linked incentive scheme plans to support 30 companies, develop 10 semiconductor IP cores and employ 200 design professionals.

The mission also emphasises design and talent development through startup support, academic programmes and national design platforms. The national EDA platform recorded 22.5 million (mn) tool hours, about 62,000 engineers have been trained and the Chips to Start up initiative targets zero point one million (mn) engineers. Indigenous microprocessor development, including the DHRUV64 family, is being advanced to reduce import dependence and support telecom, automotive and defence applications. Together these measures are intended to consolidate the ecosystem and attract private investment to scale capacity.

The Union Budget 2026–27 announced India Semiconductor Mission 2.0 (ISM 2.0), signalling a policy push to deepen domestic chip capabilities. The phase will prioritise production of semiconductor equipment and materials, full stack domestic intellectual property development and the strengthening of supply chains. A provision of Rs 10 billion (bn) has been allocated for ISM 2.0, with emphasis on industry led research and training centres to develop technology and skills. ISM 2.0 builds on earlier progress, where an incentive framework of Rs 760 bn supported silicon fabs, compound semiconductor facilities and chip design. As of December 2025, ten projects with total investment of Rs 1.6 trillion (tn) have been approved across six states, covering fabrication, advanced packaging and assembly and testing infrastructure. The roadmap targets advanced nodes and aims to position India among leading semiconductor nations by 2035. For 2026–27 the modified programme for semiconductor and display manufacturing has a total financial outlay of Rs 80 bn, aiming to accelerate capital investment, generate high quality employment and expand domestic fabrication, packaging and design capabilities. The modified fab scheme expects support for one fab with investment of Rs 40 bn and employment of 1,500 persons, while compound semiconductor and ATMP schemes envisage unit investments of Rs 110 bn and employment of 3,000 persons. The design linked incentive scheme plans to support 30 companies, develop 10 semiconductor IP cores and employ 200 design professionals. The mission also emphasises design and talent development through startup support, academic programmes and national design platforms. The national EDA platform recorded 22.5 million (mn) tool hours, about 62,000 engineers have been trained and the Chips to Start up initiative targets zero point one million (mn) engineers. Indigenous microprocessor development, including the DHRUV64 family, is being advanced to reduce import dependence and support telecom, automotive and defence applications. Together these measures are intended to consolidate the ecosystem and attract private investment to scale capacity.

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